III-V Compound Semiconductors Research Articles

Diffusion models of grown-in and implanted p-type dopant in III-V semiconductor compounds

This research shows that the diffusion of grown-in and implanted Be atoms in III-V considered semiconductor materials, such as the Liquid-Encapsulated Czochralski-grown (LEC) GaAs as well as the Gas-Source Molecular Beam Epitaxy (GSMBE) In0.53Ga0.47As, In0.73Ga0.27As0.58P0.42, In0.53Ga0.47As/In0.73Ga0.27As0.58P0.42, In0.53Ga0.47As/InP compounds, taking place during the Rapid Thermal Annealing (RTA) process, is perfectly well explained by the “full” version of the kick-out mechanism operating through singly positively ionized Be interstitials and group III self-interstitial ions (Ga, In) in all their states of positive charge including neutral. Numerical solutions of the differential equations, corresponding to the considered system of diffusion reactions, have been calculated using the finite difference approach and our elaborate finite difference-Bairstow method. Such a model naturally emerges from most research works, including ours, in the considered field, over the last decades and makes it possible to “reconcile” their different diffusion models. In this study, we also present and analyze the Secondary Ion Mass Spectrometry (SIMS) profiles of the distribution of implanted Be in GaAs at an energy of 100 keV with a high dose of 1.0 ⋅ 1015cm−2 and annealed at temperatures ranging from 700 to 850 °C for à time ranging from 60 to 240s.

Morphological and Electrical Characterization of AlGaN/GaN Heterostructures Modified By Atomic Layer Etching

Modern microelectronic components for high-power and high-frequency applications based on III-V compound semiconductors offer high break down voltage (GaN: 5 MV/cm and AlN: 15 MV/cm) at low specific on-resistance. However, it requires reliability and reproducibility of the production processes. Going to higher frequencies (5 GHz and beyond) and more integration in consumer electronics, smaller structure sizes are needed. This is going along with increasing demands on the manufacturing processes like dry etching. The main goal is to reach smaller and high controllable etching rates, going down to single atomic layers, low damage, and minimized surface roughness. Atomic layer etching (ALE) represents a key technology in order to achieve such requirements.An ALE process consists of two independent steps forming a repeatable cycle with a specific etching amount per cycle (EPC). First a surface modification is done by a chemical precursor i.e., adsorbing or oxidizing the surface. The second step is the removal of the modified layer, either physically by low energy non-reactive ion bombardment (Plasma Enhanced ALE [PEALE]) or chemically by a reactive species (Thermal ALE). The two steps are separated by an inert gas purge. This purging grants the removal of the chemistry after the first step, preventing further chemical reaction and transporting the chemical products out of the chamber after the second step.In this study, a PEALE conducted on different tools is used, for gate and contact recess study in a AlGaN/GaN heterostructure to form high electron mobility transistors (HEMT) with reduced ohmic contact resistance and threshold voltages. The results show a reduction of ohmic contact resistance at reduced forming temperatures and a linear dependence of the threshold voltage on gate recess depth. In order to determine the etching rate and roughness, atomic force microscopy (AFM) measurements were performed.The PEALE module is either integrated into a cluster tool consisting of atomic layer deposition (ALD) and chemical vapor deposition (CVD) or done in a combined ALD/ALE chamber. This opens the possibility of etching and depositing in-situ, reducing contamination and degradation of the substrate material.By this means, metal insulator semiconductor (MIS)-HEMTS with a recessed gate are studied. The monitoring of the individual processes is achieved by test structures like transfer length method structures (TLM) and metal oxide semiconductor (MOS), which showed the improved electric performance of these devices and may indicate unwanted interface issues, respectively. Additional, pre- and post-treatments could improve the interfaces further. The results will be presented and discussed in terms of ALE process development and optimization.This work was financially supported within the ALEStar project by the government of the Free-state of Saxony and the European Regional Development Fund under grant no. SAB 100402929.

Achievement of extremely small subthreshold swing in Vertical Source-All-Around-TFET with suppressed ambipolar conduction

In this manuscript, we come up with a new line-tunneling-based channel-engineered GaAsSb/GaSb heterojunction Source-All-Around Vertical Nanowire TFET (SAA-NW-VTFET) and analyzed by Sentaurus TCAD-3D simulation. In this proposed model, increased tunneling area at the source-channel interface and the n+-pocket region, along with selective III-V compound semiconductors, have boosted the ON-current in the device. On the other hand, non-uniform channel doping and reduced tunneling area at the drain end have significantly suppressed the ambipolar current. The significant results in terms of ON-current (ION = 0.789 × 10−4 A/μm), OFF-current (IOFF = 1.08 × 10−17 A/μm), ION/IOFF ratio (7.25 × 1012), threshold voltage (0.2 V), point subthreshold swing (SS = 3 mV/dec) and average SS (SSavg = 7 mV/dec) are obtained in the simulation study. In addition, the effect of temperature (250 K–450 K) on device DC characteristics and DIBT is also presented.

(Invited) Enhanced Photocatalysis on TiO2-Passivated III-V Compound Semiconductors and 2D Material Heterostructures for Water Splitting and CO2 Reduction

We report enhanced photocatalysis for H2 evolution and CO2 reduction using TiO2-passivated InP and GaAs photocathodes.1-4 The TiO2 layer makes the InP semiconductor photochemically stable. This represents a major step forward in photocatalysis, which has typically been limited to metal oxide materials. In addition to making these surfaces stable, the TiO2 film, deposited by atomic layer deposition (ALD), also provides a substantial enhancement in the efficiency of H2 evolution. We find that passivating GaAs with just a few nm of TiO2 produces a shift in the onset potential of H2 evolution by +0.35 V at 1 mA/cm2 and enhances the photocurrent by 32-fold over bare GaAs (at 0 V vs. RHE). Here, thinner TiO2 films produce a larger enhancement than thicker films, which correlates with the higher density of O-vacancies (i.e., Ti3+ surface states) observed in these thinner films using X-ray photoemission spectroscopy (XPS). While TiO2 films 1-5nm thick produce large enhancements, no enhancement is observed for TiO2 thicknesses above 10 nm, which are crystalline and, therefore, considerably more insulating than thinner amorphous TiO2 films.Using transient reflectance spectroscopy (TRS), we measure the photoexcited carrier dynamics in a GaP/TiO2 photoelectrode, as well as the electrostatic field dynamics at this semiconductor-liquid interfaces in situ under various electrochemical potentials.5 Here, the electrostatic fields at the surface of the semiconductor are measured via Franz−Keldysh oscillations (FKO). These spectra reveal that the nanoscale TiO2 protection layer enhances the built-in field and charge separation performance of GaP photoelectrodes.We also demonstrated plasmon-resonant enhancement of photocatalysis on monolayer WSe2.6 In addition, we measured the stacking dependence and resonant interlayer excitation of monolayer WSe2/MoSe2 heterostructures for photocatalytic energy conversion.7 Qiu, J., G. Zeng, M. Ge, S. Arab, M. Mecklenburg, B. Hou, C. Shen, A.V. Benderskii and S.B. Cronin, Correlation of Ti3+ states with photocatalytic enhancement in TiO2-passivated p-GaAs. Journal of Catalysis, 337, 133 (2016).Qiu, J., G.T. Zeng, M.A. Ha, M.Y. Ge, Y.J. Lin, M. Hettick, B.Y. Hou, A.N. Alexandrova, A. Javey and S.B. Cronin, Artificial Photosynthesis on TiO2-Passivated InP Nanopillars. Nano Letters, 15, 6177-6181 (2015).Qiu, J., G.T. Zeng, M.A. Ha, B.Y. Hou, M. Mecklenburg, H.T. Shi, A.N. Alexandrova and S.B. Cronin, Microscopic Study of Atomic Layer Deposition of TiO2 on GaAs and Its Photocatalytic Application. Chemistry of Materials, 27, 7977-7981 (2015).Wang, Y. and S.B. Cronin, Performance Enhancement of TiO2-encapsulated Photoelectrodes Based on III–V Compound Semiconductors, in Ultrathin Oxide Layers for Solar and Electrocatalytic Systems. 2022, Royal Society of Chemistry. p. 103-134.Xu, Z.H., B.Y. Hou, F.Y. Zhao, Z. Cai, H.T. Shi, Y.W. Liu, C.L. Hill, D.G. Musaev, M. Mecklenburg, S.B. Cronin and T.Q. Lian, Nanoscale TiO2 Protection Layer Enhances the Built-In Field and Charge Separation Performance of GaP Photoelectrodes. Nano Letters, 21, 8017-8024 (2021).Chen, J., C.S. Bailey, Y. Hong, L. Wang, Z. Cai, L. Shen, B. Hou, Y. Wang, H. Shi, J. Sambur, W. Ren, E. Pop, and S.B. Cronin., Plasmon-Resonant Enhancement of Photocatalysis on Monolayer WSe2. ACS Photonics, 6, 787 (2019).Chen, J., C.S. Bailey, D. Cui, Y. Wang, B. Wang, H. Shi, Z. Cai, E. Pop, C. Zhou and S.B. Cronin, Stacking Independence and Resonant Interlayer Excitation of Monolayer WSe2/MoSe2 Heterostructures for Photocatalytic Energy Conversion. ACS Applied Nano Materials, DOI:10.1021/acsanm.9b01898 (2020).

Ⅲ-V Compound Semiconductor Multijunction Solar Cells and their Low-Cost Manufacturing Technique

Ⅲ-V Compound Semiconductor Multijunction Solar Cells and their Low-Cost Manufacturing Technique

Preparation and Investigation of Micro-Transfer-Printable Single-Crystalline InP Coupons for Heterogeneous Integration of III-V on Si

New requirements for high-frequency applications in wireless communication and sensor technologies need III-V compound semiconductors such as indium phosphide (InP) to complement silicon (Si)-based technologies. This study establishes the basis for a new approach to heterogeneous integration of III-V on Si aimed at the transfer of single-crystalline InP coupons on Si via micro-transfer printing (μTP). The InP coupons will act as high-quality virtual substrates that allow selective homo-epitaxy. We present the chemical-mechanical polishing-based preparation and structural characterization of µm-thin (001) InP platelets, starting from high-quality 4-inch bulk crystals and micro-patterning into transferable coupons of several hundred µm2. The obtained InP platelets exhibit the desired thickness—below 10 ± 1 µm—and low surface roughness—<0.3 nm—on both sides, meeting the precondition for µTP and epitaxy. X-ray rocking curve measurements provide accurate spatial maps of the total strain, which indicate small strain variations in the µm-thin InP sample. Rocking curve mappings of the (0 0 4) reflection reveal half-widths below 16 arcsec in the majority of the sample area after thinning that is similar to commercially available InP bulk substrates. Pole figure measurements show no evidence of stress-induced micro-twinning or stacking faults. Overall, minor indications of crystal quality degradation in the product platelets, compared with the bulk samples, were detected.

Direct bonding of LiNbO3 and GaAs at room temperature by using activated Si atom layer

Heterogeneous integration of LiNbO3 and GaAs at room temperature has been achieved by using an activated Si atom interlayer, which demonstrate effectiveness in the fabrication of GaAs based LiNbO3 wafer. By using the activated Si atom interlayer as the adhesive layer, 4-inch LiNbO3 wafer is successfully directly bonded to the surface of GaAs wafer. The wafer bonding rate reaches over 95%. After bonding, the LiNbO3/GaAs bonding pair is cut into 10 × 10 mm2 square bonded chips. After annealing, the maximum bonding strength of square bonded chips exceeds 22 MPa. This means that the bonding strength of LiNbO3/GaAs wafer can be comparable to that of bulk materials. The characterization results of the bonding interface confirm that the intermediate amorphous Si layer is effective in improving the bonding strength and quality of LiNbO3/GaAs heterojunction. Heterogeneous integration of LiNbO3 with GaAs and other Ⅲ-Ⅴ compound semiconductor materials is conducive to reducing the area occupied by optical communication platforms and improving the overall efficiency of devices.

Application of TiO2/Ag/TiO2 as an Ohmic Contact to an AlGaAs Layer in a GaAs Solar Cell

This paper investigates the possibility of using a nanolaminate TiO2/Ag/TiO2 structure as a transparent conductive coating on GaAs solar cells. A novel result is that this structure forms an Ohmic contact to Al-rich AlGaAs, which is used as a “window” layer in GaAs-based solar cells. The TiO2/Ag/TiO2 structure is deposited by RF magnetron sputtering at room temperature. This nanolaminate coating has good optical and electrical properties: a high transmittance of 94% at 550 nm, a sheet resistance of 7 Ω/sq, and a figure of merit (FOM) of 105 × 10−3 Ω−1. These properties are the result of the presence of a discontinuous layer of Ag between two thin layers of TiO2. The morphology of a discontinuous layer of Ag nanogranules is confirmed by the observation of a cross-section of a sample with high-resolution transmission electron microscopy (HRTEM) and EDX analyses. Current–voltage diode characteristics of GaAs solar cells measured under standard test illumination at 1000 W/m2 are analyzed. The formation of an Ohmic contact is explained by the Fermi-level pinning effect caused by nanosized Ag particles in the nanolaminate TiO2/Ag/TiO2 structure. The obtained results demonstrate a new application of oxide−metal−oxide (OMO) coatings as Ohmic contacts to III-V compound semiconductors.

Integration Technology of Micro-LED for Next-Generation Display.

Inorganic micro light-emitting diodes (micro-LEDs) based on III-V compound semiconductors have been widely studied for self-emissive displays. From chips to applications, integration technology plays an indispensable role in micro-LED displays. For example, large-scale display relies on the integration of discrete device dies to achieve extended micro-LED array, and full color display requires integration of red, green, and blue micro-LED units on the same substrate. Moreover, the integration with transistors or complementary metal-oxide-semiconductor circuits are necessary to control and drive the micro-LED display system. In this review article, we summarized the 3 main integration technologies for micro-LED displays, which are called transfer integration, bonding integration, and growth integration. An overview of the characteristics of these 3 integration technologies is presented, while various strategies and challenges of integrated micro-LED display system are discussed.

Limiting factors for the growth rate of epitaxial III-V compound semiconductors

Limiting factors for the growth rate of epitaxial III-V compound semiconductors are investigated. A model based on the two connected diffusion equations for the group III and V adatoms applies for planar layers and different nanostructures including III-V nanowires. An expression for the step growth rate is obtained and a physical parameter is revealed which determines an element which actually limits the growth process. Keywords: III-V compound semiconductors, surface diffusion of adatoms, desorption, step growth rate.

Dielectrically Modulated III-V Compound Semiconductor Based Pocket Doped Tunnel FET for Label Free Biosensing Applications.

In this paper, a novel structure of double gate tunnel FET has been proposed and simulated for biosensing applications. The device uses III-V compound semiconductors and an n+ doped pocket at the source channel junction. Biomolecules of different dielectric constants (K) with different charge densities (Nbio), both negative and positive, are inserted in the nano-gap cavities (15 nm ×1.5 nm) that have been created under gates near source channel junction to capture biomolecules. From extensive 2D simulations, ION sensitivity of 4.351 ×108/1.03 ×108/1.514 ×109 , subthreshold swing sensitivity of 15.67/20.21/18.57 mV/dec, and threshold voltage sensitivity of 18/12/23 mV for neutral (K = 12)/negatively charged biomolecules ( [Formula: see text] C/cm2, K = 12)/positively charged biomolecules ( [Formula: see text] C/cm2, K = 12) respectively has been observed. Also, transconductance sensitivity of 9.74 ×107 and ION/IOFF sensitivity of 5.255 ×108 for neutral biomolecules (K = 12) has been calculated. Furthermore, the device performance with one-third filled cavities, two-third filled cavities and fully filled cavities has also been studied. The performance of the proposed biosensor has been compared with the previously published work and it has been observed that the sensitivity of the proposed biosensor is 100 times better than the best reported biosensor.

Modeling Insights Into the Assembly Challenges of Focal Plane Arrays

Ongoing technological advances in photodetector material growth and processing, readout integrated circuits, and robust hybridization (packaging) methods for assembling high-resolution and small-pitch size pixel arrays are the main enabling factors for pushing the frontiers of high-performance Focal Plane Array (FPA) technologies for imaging systems. This paper details the development of analytical and numerical models and demonstrates their use to generate insights into the feasibility of two flip-chip assembly processes for packaging infrared (IR) detector chips. The modelling studies focus on the challenges of forming the indium interconnection arrays in the case of the FPA technologies using Group III-V compound semiconductor materials and ultra-fine pitch pixel array layouts. The accurate alignment of the IR detector chip onto the readout chip in the case of high-density pixel architectures is a critical requirement for the packaging process. To gain better understanding of this requirement, which has a clear implication for the quality and subsequent reliability performance of the FPA, compression and reflow bonding process models are developed using suitable modeling approaches and methods and then demonstrated for two distinctive focal plane array design configurations. The novelty of this work is in the developed modeling capabilities utilizing different computational methods, from large deformation and contact analysis finite element to energy-based and harmonic motion mechanics, to characterize and optimize the mechanical and dynamic non-linear behavior of the indium solder joints and their formation during FPA packaging. The feasibility of bonding techniques for different resolution FPAs and under flip-chip misalignment conditions is assessed. The modeling results pointed to a very strict, sub-micrometer flip-chip placement accuracy requirement for the assembly of FPAs with ultra-fine indium bump array resolution.

Лимитирующие факторы скорости роста при эпитаксии полупроводниковых соединений III-V

Limiting factors for the growth rate of epitaxial III-V compound semiconductors are investigated. A model based on the two connected diffusion equations for the group III and V adatoms applies for planar layers and different nanostructures including III-V nanowires. An expression for the step growth rate is obtained and a physical parameter is revealed which determines an element which actually limits the growth process.

InAs nanowire arrays for room-temperature ultra-broadband infrared photodetection.

Detection of short-wave infrared (SWIR) and mid-wave infrared (MWIR) emissions remains challenging despite their importance in many emerging applications, including night vision, space imaging and remote sensing. III-V compound semiconductor materials such as InAs have an ideal band gap covering a spectral regime from near-infrared (NIR), SWIR to MWIR. However, due to their high dark current, InAs photodetectors normally require a low-temperature operation, which has greatly limited their practical applications. Here, we report the engineering of InAs nanowire arrays to achieve efficient photodetection of light at wavelengths ranging from NIR to MWIR (3500 nm). By using selective area metal-organic vapour-phase epitaxy, we optimise the nanowire growth temperature and V/III ratio to achieve wurtzite (WZ)-based InAs nanowire arrays with a high WZ density of ∼67%. Due to the n-type background doping of the InAs nanowires and the p-type InAs substrate used for nanowire growth, a p-n junction is formed, and an ultrawide room-temperature photoresponse ranging from 500 to 3500 nm is obtained under zero bias. It is found that the waveguide modes supported by the InAs nanowires result in a high peak responsivity of 0.44 A W-1 and a detectivity of 1.25 × 1010 cm √Hz W-1 at a wavelength of 1600 nm, a bias voltage of only -0.1 V and a relatively high operating temperature of 150 K. Such a strong light trapping effect in the InAs nanowires also leads to significantly lower reflection compared to that observed in planar photodetectors, and thus strong absorption in the substrate extending the photoresponse up to the InAs bandgap edge of 3500 nm. Our work shows that through careful material optimisation and device design, InAs nanowire arrays are promising for the development of high-performance ultra-broadband infrared photodetectors for wavelengths ranging from NIR, SWIR to MWIR.

MOVPE and its future production challenges

III-V Compound Semiconductors (CS) such as Gallium Arsenide (GaAs), Indium Phosphide (InP) and more latterly, Gallium Nitride (GaN) are critical Key Enabling Technologies, fundamentally underpinning several recent major technology revolutions. Two major current and likely-future markets within the burgeoning photonics industry ($7 billion) are 3D imaging and sensing and LIDAR applications, with high predicted market growth. Datacom and industrial markets add considerable further momentum to this market growth. Evidence of such expansion is provided in the manufacturing of VCSEL-based devices, which have in recent years, entered a rapid growth phase. For the mass-manufacturing of for example, GaAs/AlGaAs-based VCSEL MOVPE epitaxy, many areas require addressing in key underlying R&D, such as cost-reduction and in thickness and wavelength uniformity. In addition, scalability, (e.g. to 150 mm wafers), automation and in-situ process control will impact yield and throughput improvements.We will demonstrate the preparations for mass-manufacturing, through improvements implemented across the evolution of the VCSEL epiwafers from smaller diameters, through 100 mm and on to 150 mm wafers. More recently however, further developments have led to even larger diameter VCSEL wafer epitaxy, on both GaAs and Ge 200 mm substrates. Challenges in growing on such large diameter wafers will be presented from the epitaxy (layer uniformity and wafer bow) and device fabrication perspective. We will demonstrate how these improvements impact on the manufacturing readiness of production VCSEL wafers.

Isotherm Theoretical Study of the AlxGa1-xAsySb1-y Quaternary Alloy Using the Regular Solution Approximation for Its Possible Growth via Liquid-Phase Epitaxy at Low Temperatures.

This work presents the theoretical calculation of isotherm diagrams for quaternary alloys of III-V semiconductor compounds with the form IIIxIII1-xVyV1-y. In particular, the isotherm diagrams for the AlxGa1-xAsySb1-y quaternary alloy at low temperatures were calculated (500 °C, 450 °C, 400 °C, and 350 °C). The AlxGa1-xAsySb1-y quaternary alloy was formed from four binary compounds such as GaAs, AlAs, AlSb, and GaSb, all with direct bandgaps. The regular solution approximation was used to find the quaternary isotherm diagrams, represented in four linearly independent equations, which were solved using Parametric Technology Corporation Mathcad 14.0 software for different arsenic and antimony atomic fractions. The results support the possible growth of layers via liquid-phase epitaxy in a range of temperatures from 500 °C to 350 °C, where the crystalline quality could be improved at low temperatures. These semiconductor layers could have applications for optoelectronic devices in photonic communications, thermophotovoltaic systems, and microwave devices with good crystalline quality.

Laser-assisted local metal-organic vapor phase epitaxy.

Selective area epitaxial growth is an important technique, both for monolithic device integration as well as for defect reduction in heteroepitaxy of crystalline materials on foreign substrates. While surface engineering with masking materials or by surface structuring is an effective means for controlling the location of material growth, as well as for improving crystalline properties of epitaxial layers, the commonly involved integral substrate heating presents a limitation, e.g., due to constraints ofr the thermal budget applicable to existing device structures. As a solution, an epitaxial growth approach using a laser source only locally heating the selected growth area, in combination with metal-organic precursors to feed a pyrolithic chemical reaction (also known as metal-organic vapor phase epitaxy, MOVPE), is presented. Without masking or surface structuring, local epitaxial growth of III-V compound semiconductor layers on a 50-1500 µm length-scale, with high structural and optical quality, is demonstrated. We discuss general design rules for reactor chamber, laser heating, temperature measurement, sample manipulation, gas mixing, and distinguish laser-assisted local MOVPE from conventional planar growth for the important compound semiconductor GaAs. Surface de-oxidation prior to growth is mandatory to realize smooth island surfaces. Linear growth rates in the range 0.5-9 µm/h are demonstrated. With increasing island diameter, the probability for plastic deformation within the island increases, depending on reactor pressure. A step-flow mode on the island surface can be achieved by establishing a sufficiently small temperature gradient across the island.

Ultrasensitive UV-C detection based on MOCVD-grown highly crystalline ultrawide bandgap orthorhombic κ-Ga2O3

Orthorhombic κ-Ga2O3, as one of the Ga2O3 polymorphs, is considered a promising as ultrawide bandgap material for extreme environment devices. It is considered more superior than the conventional group III-V compound semiconductors and silicon carbides in extreme environments demanding material/device characteristics of high-voltage, high-temperature, high-pressure, high-impact, and high-radiation. In this study, we demonstrate ultrasensitive ultraviolet-C (UV-C) detection using Si-doped orthorhombic κ-Ga2O3 photodetectors. A 150 nm thick κ-Ga2O3 film was grown on a 2-inch diameter sapphire (α–Al2O3) wafer via metal organic chemical vapor deposition (MOCVD) method. The crystallinity of orthorhombic κ-Ga2O3 film was investigated by X-ray diffraction (XRD) and transmission electron microscopy (TEM). The ultrawide bandgap of approximately 4.9 eV was confirmed by UV transmittance measurement. For UV-C detection analysis, a planar device with a channel length of 20 μm was fabricated using Au/Ti metal contacts on the orthorhombic κ-Ga2O3 film. The device doped under 15 sccm SiH4 flow rate showed ultrahigh photoresponse of ∼72.1 A/W, Ion/Ioff of ∼14, and decent rise (∼0.35 s) and decay (∼1.79 s). Our results will contribute to the understanding on a new material phase of κ-Ga2O3, as well as on developing optoelectronics devices with high radiation hardness suitable for operation in extreme environments.

Transfer Printable Single-Crystalline Coupons for III-V on Si Integration

The next-generation internet (6G) requires highly functional devices that e.g. realize frequencies in the THz range for higher data rates and lower latencies. Those requirements exceed the physical limits of established CMOS technologies based on silicon (Si). Hence, there is demand for other semiconductor materials with superior electronic and optical properties that complement Si. One of the key candidates is the III-V compound semiconductor, indium phosphide (InP). Due to its high electron mobility and direct band gap, InP-based devices allow access to frequencies >100 GHz and operate at the optical fibre compatible wavelength of 1.55 μm.1 With the perspective of leveraging the advantages of Si-based CMOS technology and III-V semiconductors, hetero-integration of III-V materials on Si is of great interest. However, existing integration approaches entail certain disadvantages: (i) High dislocation densities due to the lattice mismatch of InP and Si for integration via hetero-epitaxial growth;2 (ii) limited integration density and the requirement of accurate alignment for flip-chip integration; and (iii) high process-related losses of Si and III-V materials as well as thermal stress and low thermal conductivity of adhesive layers degrading device performance for wafer/die bonding technologies.3 Another promising approach for III-V-on-Si integration is micro-transfer-printing (μTP) that involves pick-up and transfer of µm-small chips from a source substrate to a target substrate with high alignment accuracy by using an elastomeric stamp. Advantages of μTP are high integration densities and efficient material use. The technique was already implemented for III-V-on-Si photonic integrated circuits by transfer of epitaxial III-V layers.4 However, using sacrificial III-V interlayers for release and adhesives for bonding still leads to transfer issues and low operation temperature for the devices, respectively.We pursue a new approach to hetero-integration of III-V on Si that aims at the transfer of single-crystalline InP coupons onto Si via μTP. This will be achieved by obtaining crystalline coupons with a thickness of d ≤ 10 µm and two polished surfaces that attain low roughness, needed i.a. for µTP. If the high structural quality of the single-crystalline InP source material can be maintained, this process will provide high quality templates for subsequent epitaxial growth. Towards this goal, we developed a sophisticated micro-preparation process in cooperation with the Leibniz Institute for High Performance Microelectronics IHP.5 Starting from 4-inch single crystals with homogeneous, low dislocation density of 2×103 cm- 2 grown at IKZ,6 thinned InP dies were obtained by sawing, grinding and employing an optimized two-step chemical mechanical polishing (CMP). In order to produce µm-sized transfer-printable coupons, the InP dies were micro structured by means of photolithography assisted patterning and wet (under-)etching (Fig. 1). The coupons can then be picked up with a stamp and transferred to the target wafer. Main innovation of this process is the resin which serves as low stress fixing layer for CMP as well as sacrificial layer for later release.The optimized CMP process with abrasive-free final polishing yielded InP platelets of the desired thickness below 10 μm with low thickness deviation < 1 µm and excellent surface roughness of S q ≈ 0.3 nm (Fig. 2a,b,d). This value even meets the requirements for adhesive-free bonding (S q ≤ 2 nm) and subsequent epitaxial growth (S q ≤ 0.5 nm). X-ray rocking curve mapping provides accurate spatial maps of lattice deformations in the material that may be a consequence of the mechanical processing. Rocking curve widths mappings of the 004 reflection of a (001) sample before and after thinning are homogeneous and below 25 arcsec in the majority of the sample area. Overall no signs of systematic crystal quality deterioration in the product platelets compared to bulk samples have been detected.In summary, the feasibility of μm-thin InP platelet fabrication was demonstrated. Final platelets meet the prerequisites of low and uniform thickness, high planarity, low roughness and little crystal quality deterioration. Furthermore, first InP platelets could successfully be patterned to 100–400 µm-sized coupons using optical lithography and wet etching (Fig. 2c). This opens a path to take the next steps towards hetero-integration on Si by means of µTP with high potential for adhesive-free bonding.

Perspectives on the Development of Metalorganic Vapor Phase Epitaxy for III-V Optoelectronic Devices

The mainstream production of optoelectronic and electronic devices based on epitaxial III-V compound semiconductor materials largely employs metalorganic vapor phase epitaxy, a process first demonstrated for devices in the 1970’s. For this special issue in honor of Prof. P. Daniel Dapkus, this paper first briefly reviews his early contributions that spearheaded the interest of MOVPE as a III-V device epitaxy process. Next, the paper discusses MOVPE reactor development in the 1980’s, which at the time was one of the key challenges in establishing MOVPE technology as a reliable epitaxy manufacturing process. The approach combined physical modeling and numerical simulations of reactor processes followed by materials and device demonstrations. Highly uniform performance metrics of AlGaAs/AlGaAs quantum-well diode lasers and two-dimensional monolithic surface-emitting lasers were demonstrated with excellent run-to-run reproducibility. This foundational approach advanced efforts to standardize reactors and subsequent scaling for high-throughput production.